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s6bp202a assp, 42v, 2.4a, synchronous buck - boost dc/dc converter ic cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 08496 rev. *d revised october 13, 2017 s6bp202a is a 1 - c h buck - b oost dc/dc converter ic with four built - in switching fets. th is ic is able to supply up to 2.4a of load current within the very wide range from 2.5v to 42v in the input voltage . this ic has an operation mode that is automatically changed to pfm operation during low load , which can achieve super - high efficiency with a very low quiescent current 20 a . it is possible to provide stable output voltage from an automo tive cold cranking and load dump , up to 42v, conditions within 1 ms transition time. as a result, this ic is suitable for power supply solutions of a utomotive and industrial applications. this ic has the sync function , which is capable of selecting the syn c_in that is able to inputs an external clock signal or the sync_out that is able to output an internal clock. when selecting the sync_in and an external clock signal in the range from 200 khz to 400 khz is inputted, the fets perform the switching operation with s ynchroniz ing signal from an ext ernal clock . when selecting the sync_in and an external clock signal is not inputted, t he fets perform the switching operation from an internal clock . when selecting the sync_out, this ic provides a clock signal generated inside to external devices . the internal clock signal i n the range from 200 khz to 2.1 m hz can be set by an external r esistor . s ince external voltage setting resistors and phase compensation capacitors are not required wi th this ic, it can reduce the number of parts and a part mounting area . this ic has five protection functio ns , input u nder v oltage l ock o ut ( input uvlo), output u nder v oltage p rotection ( output uvp), output o ver v oltage p rotection ( output ovp), output o ver c urrent p rotection ( output ocp), and t hermal s hutdown (tsd). moreover, this ic has the power g ood (pg) function that indicate s the state of the output voltage ( vout pin). when the output voltage reaches the pg voltage, the pg signal is outputted . also, th e power - on reset time for the pg signal is selectable. the vout output voltage, sync function, vout uvp t hreshold , vout o vp t hreshold , p ower - on r eset t ime of t h is product are selectable from the product lineup ( r efer to the " 1 . product lineup " ). features ? wide i nput v oltage r ange: 2.5v to 42v ? s electable o utput v oltage (f actory set table): 5.0 00v/5.050v/5.075v/5.100v/5.125v/5.150v/5.200v ? wide o perating f requency r ange : 200 khz to 2.1 mhz ? e xternal s ynchronized c lock r ange : 200 khz to 400 khz ? sync function (f actory set table) ? syn c_in: e xternal c lock input ( unless input ting clock, this ic operates by i nternal clock ) ? syn c_out: in ternal c lock output ? super - h igh e fficiency by pfm o peration (when setting mode pin to a low level ) ? a utomatic pwm/pfm s witching operation and fixed pwm operation are selectable by mode pin ? b uilt - in switching fet ? synchronous c urrent m ode a rchitecture ? shutdown c urrent : lower than 1 a ? quiescent c urrent : 20 a ? power good monitor ? output voltage m onitoring by w indow c omparator ? power - on reset t ime (f actory set table) : 7 s, 14 ms ? soft s tart t ime without l oad d ependence : 0.9 ms (when switching f requency = 2.1 mhz) ? enhanced p rotection f unctions ? input uvlo ? output uvp (f actory set table) : 92.0%, 95.5% ? output ovp (f act ory set table): 108.0%, 104.5% ? output ovc ? thermal s hutdown ? small e tssop 16 package (e xposed pad ): 5 mm 6.4 mm ? aec - q100 compliant (grade - 1) applications ? instrument c luster ? advanced d river a ssistance s ystems (adas) ? gateway m odule ? automotive a pplications ? industrial a pplications block diagram b u c k - b o o s t d c / d c c o n v e r t e r 2 . 1 m h z p o w e r g o o d 5 v l d o , e n a b l e o s c , e x t e r n a l s y n c p r o t e c t i o n 5 v b a t t e r y 2 . 5 - 4 2 v e n a b l e p o w e r g o o d p w m / p f m e x t e r n a l c l o c k f o r f r e q u e n c y s e t t i n g s y n c h r o n i z a t i o n / s w i t c h g n d s 6 b p 2 0 2 a 5 v / 2 . 4 a i n t e r n a l c l o c k o u t p u t
document number: 002 - 08496 rev. *d page 2 of 20 s6bp202a more information cypress provides a wealth of data at www.cypress.com/pmic to help you to select the right pmic device for your design, and to help you to quickly and effectively integrate the device into your design. following is an abbreviated list for s6bp 2 0 2 a . ? overview: automotive pmic portfolio , automotive pmic roadmap ? product selector: ? s6bp202a : 1 - c h buck - boost automotive pmic ? application notes: cypress offers s6bp 2 0 2 a application notes. recommended application notes for getting started with s6bp 202 a are: ? an 99497 : desi gning a power management system with s6bp201a, s6bp202a, and s6bp203a ? an201006 : thermal considerations and parameters ? evaluation kit operation manual: ? s6sbp202a1fva1001 : power block of automotive instrument cluster ? related products: ? s6bp201a , s6bp203a : 1 - c h buck - boost automotive pmic ? s6bp401a : 6 - c h automotive pmic for adas ? s6bp501a, s6bp502a : 3 - c h automotive pmic for instrument cluster
document number: 002 - 08496 rev. *d page 3 of 20 s6bp202a contents features ................................ ................................ ................................ ................................ ................................ ................... 1 applications ................................ ................................ ................................ ................................ ................................ ............ 1 block diagram ................................ ................................ ................................ ................................ ................................ ......... 1 more information ................................ ................................ ................................ ................................ ................................ .... 2 1. product lineup ................................ ................................ ................................ ................................ ............................... 4 2. pin assignment ................................ ................................ ................................ ................................ .............................. 5 3. pin descriptions ................................ ................................ ................................ ................................ ............................. 5 4. archite cture block diagram ................................ ................................ ................................ ................................ .......... 7 5. absolute maximum ratings ................................ ................................ ................................ ................................ .......... 8 6. recommended operating conditions ................................ ................................ ................................ .......................... 8 7. electrical characteristics ................................ ................................ ................................ ................................ .............. 9 8. functional description ................................ ................................ ................................ ................................ ................ 10 8.1 block description ................................ ................................ ................................ ................................ ......................... 10 8.2 protection function table ................................ ................................ ................................ ................................ ............ 11 9. application circuit example and parts list ................................ ................................ ................................ ................ 12 10. application note ................................ ................................ ................................ ................................ ........................... 13 10.1 setting the operation conditions ................................ ................................ ................................ ................................ . 13 11. reference data ................................ ................................ ................................ ................................ ............................. 15 12. usage precaution ................................ ................................ ................................ ................................ ......................... 17 13. rohs compliance information ................................ ................................ ................................ ................................ ... 17 14. ordering information ................................ ................................ ................................ ................................ ................... 17 15. package dimensions ................................ ................................ ................................ ................................ ................... 18 16. major changes ................................ ................................ ................................ ................................ ............................. 19 document history ................................ ................................ ................................ ................................ ................................ . 19 sales, solutions, and legal information ................................ ................................ ................................ ............................. 20
document number: 002 - 08496 rev. *d page 4 of 20 s6bp202a 1. product lineup t he vout output v oltage, sync f unction, vout uvp t hreshold , vout o vp t hreshold , p ower - on r eset t ime of t h is product are set at the factory shipment . to order a product, select an item from the product lineup blow . part number ( mpn ) order code vout o utput v oltage [ v] sync function vout uvp threshold [ %] vout o vp threshold [%] p ower - on r eset time[ s] falling (typ) rising (typ) rising (typ) falling (typ) s6bp202a1bst2b00a 1b 5.000 sync_in 92.0 93.0 108.0 107.0 7 .0 S6BP202A1CST2B00A 1c sync_out s6bp202a1dst2b00 a 1d sync_in 95.5 96.5 104.5 103.5 s6bp202a1est2b00a 1e sync_out s6bp202a1fst2b00 a 1f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a1gst2b00 a 1g sync_out s6bp202a1hst2b00 a 1h sync_in 95.5 96.5 104.5 103.5 s6bp202a1jst2b00a 1j sync_out s6bp202a2bst2b00 a 2b 5.050 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a2cst2b00 a 2c sync_out s6bp202a2dst2b00 a 2d sync_in 95.5 96.5 104.5 103.5 s6bp202a2est2b00a 2e sync_out s6bp202a2fst2b00 a 2f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a2gst2b00 a 2g sync_out s6bp202a2hst2b00 a 2h sync_in 95.5 96.5 104.5 103.5 s6bp202a2jst2b00 a 2j sync_out s6bp202a3bst2b00 a 3b 5.075 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a3cst2b00 a 3c sync_out s6bp202a3dst2b00 a 3d sync_in 95.5 96.5 104.5 103.5 s6bp202a3est2b00 a 3e sync_out s6bp202a3fst2b00 a 3f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a3gst2b00 a 3g sync_out s6bp202a3hst2b00 a 3h sync_in 95.5 96.5 104.5 103.5 s6bp202a3jst2b00a 3j sync_out s6bp202a4bst2b00a 4b 5.100 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a4cst2b00a 4c sync_out s6bp202a4dst2b00a 4d sync_in 95.5 96.5 104.5 103.5 s6bp202a4est2b00a 4e sync_out s6bp202a4fst2b00a 4f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a4gst2b00a 4g sync_out s6bp202a4hst2b00a 4h sync_in 95.5 96.5 104.5 103.5 s6bp202a4jst2b00a 4j sync_out s6bp202a5bst2b00a 5b 5.125 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a5cst2b00a 5c sync_out s6bp202a5dst2b00a 5d sync_in 95.5 96.5 104.5 103.5 s6bp202a5est2b00a 5e sync_out s6bp202a5fst2b00a 5f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a5gst2b00a 5g sync_out s6bp202a5hst2b00a 5h sync_in 95.5 96.5 104.5 103.5 s6bp202a5jst2b00a 5j sync_out s6bp202a6bst2b00a 6b 5.150 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a6cst2b00a 6c sync_out s6bp202a6dst2b00a 6d sync_in 95.5 96.5 104.5 103.5 s6bp202a6est2b00a 6e sync_out s6bp202a6fst2b00a 6f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a6gst2b00a 6g sync_out s6bp202a6hst2b00a 6h sync_in 95.5 96.5 104.5 103.5 s6bp202a6jst2b00a 6j sync_out
document number: 002 - 08496 rev. *d page 5 of 20 s6bp202a part number ( mpn ) order code vout output v oltage [ v] sync function vout uvp threshold [ %] vout o vp threshold [%] p ower - on r eset time[ s] falling (typ) rising (typ) rising (typ) falling (typ) s6bp202a7bst2b00a 7b 5.200 sync_in 92.0 93.0 108.0 107.0 7 .0 s6bp202a7cst2b00a 7c sync_out s6bp202a7dst2b00a 7d sync_in 95.5 96.5 104.5 103.5 s6bp202a7est2b00a 7e sync_out s6bp202a7fst2b00a 7f sync_in 92.0 93.0 108.0 107.0 14.0m s6bp202a7gst2b00a 7g sync_out s6bp202a7hst2b00a 7h sync_in 95.5 96.5 104.5 103.5 s6bp202a7jst2b00a 7j sync_out mpn: marketing part number 2. pin assignment figure 2 - 1 pin assignment ( top view) ( sec016) 3. pin descriptions table 3 - 1 pin descriptions pin no. pin name i/o description 1 pgnd1 ? gnd pin for b uilt - in switching fe t 2 lx1 o inductor connection pin 3 pvin i power supply pin for pwm controller and switching fets 4 bst i bst (boost) capacitor connection pin 5 vin i power supply pin 6 ena i dc/dc converter enable pin 7 mode i pwm /pfm operation control pin 8 vcc o v cc capacitor connection pin . ldo output pin of internal reference voltage 9 gnd ? gnd pin 10 pg o o pen drain output pin for power good . when b eing used, connect pg pin to vcc pin or vout pin. w hen not being used, leave pg pin open. 11 sync i/o ext ernal clock input pin / internal clock output pin for the sync pin setting, refer to " 10.1 setting the operation conditions " 12 rt o timing r esist or connection pin for internal clock (switching frequency ) for the resist ance, refer to " 10.1 setting the operation conditions " 13 fb i output voltage feed back pin 14 vout o dc/dc converter output pin 15 lx2 o inductor connection output pin. 16 pgnd2 ? gnd pin for b uilt - in switching fe t ep gnd ? gnd pin 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 e p : g n d p g n d 1 l x 1 p v i n b s t v i n e n a m o d e v c c p g n d 2 l x 2 v o u t f b r t s y n c p g g n d
document number: 002 - 08496 rev. *d page 6 of 20 s6bp202a figure 3 - 1 i /o pin equivalent circuit diagram < vin pin, pvin pin> < lx1 pin , bst pin > < vout pin, lx2 pin> < ena pin> < mode pin> < sync pin> < rt pin> 5 v i n 1 6 p g n d 2 3 p v i n 9 g n d 1 p g n d 1 3 p v i n 1 p g n d 1 8 v c c 4 b s t 2 l x 1 1 6 p g n d 2 1 4 v o u t 1 5 l x 2 9 g n d 1 3 f b 8 v c c 5 v i n 1 3 f b 9 g n d 9 g n d 1 0 p g 5 v i n 6 e n a 9 g n d 8 v c c 7 m o d e 9 g n d 8 v c c 1 1 s y n c 9 g n d 8 v c c 9 g n d 1 2 r t
document number: 002 - 08496 rev. *d page 7 of 20 s6bp202a 4. architecture block diagram figure 4 - 1 a rchitecture block diagram s y n c b g r 5 v l d o v i n u v l o t s d l s s l o p e b o o s t m o d e p u l s e p w m l o g i c b y p a s s s w v c c u v l o o s c v i n 5 e n a 6 g n d 9 c k 1 3 f b v o u t 1 4 v o u t 1 5 l x 2 f b v i n l s c k i c m p p f m c m p v c c p g n d 1 1 p g 1 2 r t 8 v c c h i g h s i d e f e t 2 l o w s i d e f e t 2 1 6 p g n d 2 l o w s i d e f e t 1 h i g h s i d e f e t 1 b s t 4 l x 1 2 p v i n 3 v i n s y n c m o d e 1 1 s y n c 7 m o d e e r r a m p 1 0 p g b u c k - b o o s t d c / d c c o n v e r t e r
document number: 002 - 08496 rev. *d page 8 of 20 s6bp202a 5. absolute maximum ratings parameter symbol condition rating unit min max power s upply v oltage (*1) v vin vin pin ? 0.3 +48.0 v v pvin pvin pin ? 0.3 +48.0 v v vcc vcc pin ? 0.3 +6.9 v terminal v oltage(*1) v bst bst pin ? 0.3 +48.0 v v lx1 lx1 pin ? 2.0 +48.0 v v lx2 lx2 pin ? 2.0 +6.9 v v fb fb pin ? 0.3 v vcc v v rt rt pin ? 0.3 v vcc v v mode mode pin ? 0.3 v vcc v v sync sync pin ? 0.3 v vcc v v ena ena pin ? 0.3 +48.0 v v pg pg pin ? 0.3 +6.9 v difference v oltage(*1) v bst - lx between bst C lx1 pins ? 0.3 +6.9 v v gnd between gnd C pgnd1 pins , between gnd C pgnd2 pins ? 0.3 +0.3 v pg output current i pg pg pin ? 3 0 ma po wer d issipation (*1) p d ta 25 c 0 3324 (*2) mw storage t emperature t stg ? ? 55 +150 c * 1: when pgnd1 = pgnd2 = gnd = 0v *2: when the product is mounted on 76.2 mm 114.3 mm, four - layer fr - 4 board w arning : 1. semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. 6. recommended operating conditions paramet er symbol condition value unit min typ max power supply voltage (*1) v vin vin pin at start - up 5.0 12.0 42.0 v after start - up 2 .5 12.0 42.0 v terminal voltage (*1) v bst bst pin 0.0 ? 47.5 v v lx1 lx1 pin ? 1.0 + 12.0 + 42.0 v v lx2 lx2 pin ? 1.0 ? + 5.5 v v fb fb pin 0.0 ? 5.5 v v mode mode pin 0.0 ? 5.5 v v sync sync pin 0.0 ? 5.5 v v ena ena pin 0.0 12.0 42.0 v v pg pg pin 0.0 ? 5.5 v difference voltage(*1) v bst - lx1 between bst ? lx1 pins 0.0 ? 5.5 v v gnd between gnd ? pgnd1 pins, between gnd ? pgnd2 pins ? 0.05 0.00 + 0.05 v pg output current i pg pg pin (sink current) 0 ? 1 ma bst capacitance c bst between bst ? lx1 pins 0.068 0.100 0.470 f vcc capacitance c vcc between vcc ? gnd pins 2.2 4.7 10.0 f timing r esistance r rt between rt ? gnd pins . when using internal clock 22 ? 270 k operating a mbient t emperature ta ? ? 40 +25 +125 c *1: when pgnd1 = pgnd2 = gnd = 0v w arning : 1. the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. any use of semiconducto r devices will be under their recommended operating condition. 3. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 08496 rev. *d page 9 of 20 s6bp202a 7. electrical characteristics vin=pvin=12v, ena=5v (unless spe cified otherwise, these are the electrical characteristics under the recommended operating environment.) parameter symbol condition value unit min typ max buck - b oost dc/dc c onverter b lock vout output v oltage v vout i vout = 0a , when v vout = 5.000 (*1) 4.925 5.000 5.075 v i vout = 0a , when v vout = 5.050 (*1) 4.975 5.050 5.125 v i vout = 0a , when v vout = 5.075 (*1) 4.999 5.075 5.151 v i vout = 0a , when v vout = 5.100 (*1) 5.024 5.100 5.176 v i vout = 0a , when v vout = 5.125 (*1) 5.048 5.125 5.201 v i vout = 0a , when v vout = 5.150 (*1) 5.073 5.150 5.227 v i vout = 0a , when v vout = 5.200 (*1) 5.122 5.200 5.278 v fb input resistance r fb en = 0v, ta = +25 c 3.84 4.80 5.76 m switching fet o n - resistance r hsidefet1 lx1 = ? 30 ma (between pvin ? lx1) ? 150 ? m r lsidefet1 lx1 = 30 ma ( between lx1 ? pgnd1) ? 150 ? m r hsidefet2 lx2 = ? 30 ma (between vout ? lx2) ? 150 ? m r lsidefet2 lx2 = 30 ma ( between lx2 ? pgnd2) ? 150 ? m s witching fet l eakage current i leak ? ? ? 5 a soft - start t ime t ss r rt = 22 k 0.855 0.9 0.945 ms maximum output current i vout pvin 7.5v, ta = 25 c 2.4 (*2) ? ? a pvin = 4.5v, ta = 25 c 1.0 (*2) ? ? a current l imit i limt pvin = 12v, l = 2.2 h 2.4 (*2) ? ? a 5v ldo block vcc output voltage v vcc vin = 12v 4.9 5.0 5.1 v vin uvlo b lock vin uvlo falling t hreshold v uvlovinhl vin input voltage when falling 2.30 2.4 0 2.50 v vin uvlo rising t hreshold v uvlovinlh vin i nput voltage when rising 4.55 4.75 4.95 v vcc uvlo b lock vcc uvlo falling t hreshold v uvlovcchl vcc input voltage when falling 2.30 2.4 0 2.50 v vcc uvlo rising t hreshold v uvlovcclh vcc input voltage when rising 4.55 4.75 4.95 v ena pin enable c ondition v ena enable voltage range 1.10 ? v vin v v dsb disable voltage range 0.0 ? 0.2 v ena input current i ena v ena = 12v ? 1 3 a mode pin mode input voltage v mode_l a utomatic pwm/pfm s witching 0.0 ? 0.4 v v mode_h fixed pwm operation 2.0 ? v vout v mode input current i mode mode = 5.0v ? 5 10 a osc block s witching f requency (sync output f requency ) f osc r rt = 22k 2.0 2.1 2.2 mhz r rt = 270k 180 200 220 khz sync block (sync_in/ sync_out) sync input t hreshold v sync_l w hen selecting sync_in (*1) 0.0 ? 0.4 v v sync_h w hen selecting sync_in (*1) 2.0 ? v vout v sync input f requency v sync_l w hen selecting sync_in (*1) 200 ? 400 khz sync input duty ratio v sync_h w hen selecting sync_in (*1) +20 +50 +80 % sync output frequency f output w hen selecting sync_ out (*1) ? f osc ? hz sync output duty r atio f outduty w hen selecting sync_ out (*1) +40 +50 +60 % sync leakage current i lksync v sync = 5.0v, w hen selecting sync_in (*1) ? 5 10 a pg block ( uvp, ovp) vout uvp falling t hreshold p guvphl falling t hreshold for vout o utput v oltage s etting (*1) 90.5 92.0 93.5 % 94.0 95.5 97.0 % vout uvp rising t hreshold p guvplh rising t hreshold for vout o utput v oltage s etting (*1) 91.5 93.0 94.5 % 95.0 96.5 98.0 % vout ovp rising t hreshold p govplh rising t hreshold for vout o utput v oltage s etting (*1) 106.5 108.0 109.5 % 103.0 104.5 106.0 % vout ovp falling t hreshold p govphl falling t hreshold for vout o utput v oltage s etting (*1) 105.5 107.0 108.5 % 102.0 103.5 105.0 % l eak current i lkpg v pwrgd = 5.0v, v ena = 0v 0 ? 1 a low l evel output voltage v olpg i pgsink = 1 ma 0.025 0.05 0.15 v delay t ime at abnormal detection t ppg at power shutdown ? 7 (*2) 12 (*2) s power - on r eset time (*1) t rpg at power good ? 7 (*2) 12 (*2) s 9.1 14.0 18.9 ms
document number: 002 - 08496 rev. *d page 10 of 20 s6bp202a parameter symbol condition value unit min typ max thermal shutdown b lock (tsd) shut down temperature t tsdh ? ? 165 (* 2) ? c t tsdl hysteresis ? 10 (*2) ? c supply current shutdown c urrent i vinsdn vin input current, v ena = 0v ? 1 5 a q uiescent current i vinq vin input current, v ena = 12v, i vout = 0a , mode/sync/pg pins = open ? 20 40 a *1: refer to " 1 . product lineup " * 2: the electrical characteristic is ensured by statistical characterization and indirect tests. 8. functional description 8.1 block description input u nder v oltage lockout (input uvlo ) the input uvlo is the function that prevent s a malfunction of this ic from the following status , and protects post stage devices . ? transitional state at start - up ? momentary drop of power supply voltage to prevent such a malfunction , this protection monitors the vin inp ut voltage and vcc voltage. when either vin or vcc voltage falls to the uvlo falling t hreshold , 2.4v (typ), or lower, the ic stops the vout voltage output and becomes uvlo status . when both vin and vcc voltages reach the uvlo rising t hreshold , 4.75v (typ), or higher, the ic is released from the uvlo state and returns to the normal operation. output under voltage protectio n (output uvp) the output uvp is the function that monitors the voltage drop of the vout pin and notifies by the pg pin. when the output voltage falls to the uvp falling t hreshold (p guvphl ) for the o utput v oltage s etting or lower, the pg voltage is fixed to the low level. t he ic becomes the uv p status , but the switching operation is maintained under the uvp status . when the output voltage once again reaches the uvp rising t hreshold (p guvplh ) for the o utput v oltage s etting or higher, the ic is released from the uvp state and the pg voltage is fixed to the high level. output over voltage protection ( output o vp ) the output o vp is the function that monitors the voltage rise of the vout pin and stops the switching operation s, which protects poststage devices from overvoltage . also, the vout state is notified by the pg pin . when the output voltage rises to the o vp falling t hres hold (p go vp lh ) for the o utput v oltage s etting or higher , th e pg voltage is fixed to the low level. the ic becomes the o vp status , and the switching operation s of the high - side fets are stopped. when the output voltage once again falls to the o vp falling t hreshold (p g o vp hl ) for the o utput v oltage s etting o r lower , the ic is released from the o vp state and resumes the switching operation s. t he pg voltage is fixed to the high level again . output over current protection ( output ocp) the output ocp is the function that limits the excessive current load and protects poststage device s. thermal shutdown (tsd) the tsd is the function that protects the ic from heat - destruction. when the junction temperature reaches +165c (typ) , the h ig h - side and l ow - si de switching fet are turned off and t he ic becomes the tsd status . when the junction temperature once again falls to +155c (typ) or lower , the ic is released from the tsd state and restart s the power supply .
document number: 002 - 08496 rev. *d page 11 of 20 s6bp202a 8.2 protection function table the following table shows the state of each pin when each protection function operates. table 8 - 1 protection function table f unction ena pin setting pg pin output dc/dc converter operation remarks shutdown operation l h i - z (*1) shutdown it is recommended to connect pg pin to vcc pin or vout pin via a pull - up resistor. when setting ena pin to a low level, both vcc pin and vout pin voltage s drop to 0v. therefore, pg pin outputs 0v. nominal operation h h i - z (*1) switching ? input u nder voltage protection ( input uvlo) h l shutdown after releasing uvlo state, this ic is automatically reset with soft start. output u nder voltage protection ( output uvp) h l switching ? output o ver voltage protection ( output ovp) h l shutdown ? output o ver c urrent protection ( output ocp ) h l switching ocp operates to drop the output voltage. thermal s hutdown (tsd) h l shutdown after releasing tsd state, this ic is automatically reset with soft start. * 1 : pg pin is formed as an open drain structure. the internal mosfet is in the off state .
document number: 002 - 08496 rev. *d page 12 of 20 s6bp202a 9. application circuit example and parts list figure 9 - 1 application circuit example table 9 - 1 parts list symbol item value part number vendor package size (w l h[mm]) remarks c vin , c bst c eramic c apacitor 0.1 f cga2b3x7r1h104k050bb tdk 1.0 0.5 0.5 x7r, rated v oltage : 50 vdc c pvin c eramic c apacitor 1 0 f cga9n3x7r1h106k230kb tdk 5.7 5.0 2.3 x7r, rated v oltage : 50 vdc c vcc c eramic c apacitor 4.7 f cga4j3x7r1c475k125ab tdk 2 . 01 . 2 5 1 . 2 5 x7r, rated v oltage : 16 vdc c vout_1 , c vout_2 c eramic c apacitor 22 f cga6p1x7r1c226m250ac tdk 3.2 2.5 2.5 x7r, rated v oltage : 16 vdc l lx i nductor 2.2 h clf7045t - 2r2n - d tdk 7.2 6.9 4.5 dcr: 14.6 m , i dc_max : 5.5a r rt resistor 22 k rk73h1jttd2202f koa 0.8 1.6 0.45 ? r pg resistor 1 m rk73h1jttd100 4 f koa 0.8 1.6 0.45 ? tdk: tdk corporation koa: koa corporation r r t 5 8 1 3 7 1 1 6 1 2 9 e p v o u t v c c v i n 2 2 k c v c c 4 . 7 f c v i n 0 . 1 f 3 4 p v i n 2 1 5 l l x 2 . 2 h c b s t 0 . 1 f v i n c p v i n 1 0 f 1 6 1 0 1 1 4 c v o u t _ 1 2 2 f v c c o r v o u t v o u t m o d e s y n c e n a p g v o u t c v o u t _ 2 2 2 f f o s c = 2 . 1 m h z w h e n s e l e c t i n g v o u t o u t p u t v o l t a g e = 5 . 0 v v i n v c c f b m o d e s y n c e n a r t g n d g n d b s t l x 1 l x 2 v o u t p g n d 1 p g n d 2 p g s 6 b p 2 0 2 a r p g 1 m
document number: 002 - 08496 rev. *d page 13 of 20 s6bp202a 10. application note 10.1 setting the operation conditions operation state of dc/dc c onvertor when selecting sync_in the operation stage of dc/cd c onverter is set by both mode pin and sync pin . table 10 - 1 operation state of dc/dc c onvertor when selecting sync_in mode pin sync pin ( signal input) operation state of dc/dc c onvertor l (* 3) l (* 3) a utomatic pwm/pfm s witching operation from an internal clock ext ernal c lock input (*5) fixed pwm operation with s ynchroniz ing signal from an ext ernal clock (*2) h (* 4) prohibition of u se (*1) h (* 4) l (* 3) fixed pwm operation from an internal clock ext ernal c lock input (*5) fixed pwm operation with s ynchroniz ing signal from an ext ernal clock (*2) h (* 4) prohibition of u se (*1) * 1 : when selecting sync_in and setting sync pin to a high level, the q uiescent c urrent ( i vinq ) is increased . * 2 : set the t iming r esistance (r rt ) to 3 30 k . * 3 : a pply the gnd1 or gnd2 voltage . * 4 : a pply the vout voltage. * 5 : a pply the vout voltage at a high level . a pply the gnd1 or gnd2 voltage at a low level operation state of dc/dc c onvertor when selecting sync_out when selecting sync _out, the phase of sync clock output is shifted from an internal clock. table 10 - 2 operation state of dc/dc c onvertor when selecting sync_out mode pin sync pin operation state of dc/dc c onvertor l (*1) in t ernal c lock output fixed pwm operation from an internal clock h (*2) * 1: a pply the gnd1 or gnd2 voltage . *2: a pply the vout voltage. setting of switching f requency ( internal clock) the switching frequency ( internal clock) can be set by r t r esist or, which value is the timing r esist ance ( r rt ) , connected to rt pin . set the timing r esi st ance in a range within the following graph figure 10 - 1 f osc vs r rt m easured c haracteristic f o s c v s r r t m e a s u r e d c h a r a c t e r i s t i c f o s c [ m h z ] r r t [ k s 6 b p 2 0 2 a g r a p h 0 0 1 1 . 0 1 . 5 2 . 0 2 0 0 3 0 0
document number: 002 - 08496 rev. *d page 14 of 20 s6bp202a the reference value can be calculated by the following formula. f osc [ hz ] 1 r rt 21 . 7 10 ? 12 f osc : switching f requency [hz] r rt : timing r esist ance [ ] setting of s oft - s tart t ime the s oft - s tart t ime is determined by the timing r esistance ( r rt ) , the value of the resistor con nect ed to rt pin . t ss [ s ] = 1 f osc 2 1024 t ss : soft - start time [s] f osc : switching frequency [hz] c onsideration of vout m aximum o utput c urrent make sure the vout maximum output current in a range within the following graph . figure 10 - 2 i vout vs v vin i v o u t v s v v i n i v o u t [ a ] v v i n [ v ] 0 0 . 0 3 . 0 1 2 0 . 5 1 s 6 b p 2 0 2 a g r a p h 0 0 2 1 . 0 1 . 5 2 . 0 2 3 4 5 6 7 8 1 0 1 1 9 2 . 5 t a = + 2 5 o c , f o s c = 2 . 1 m h z t a = + 1 2 5 o c , f o s c = 2 . 1 m h z
document number: 002 - 08496 rev. *d page 15 of 20 s6bp202a 11. reference data the followings are the reference data measured under the conditions shown in 9 . application circuit example and parts list . e f f i c i e n c y [ % ] l o a d c u r r e n t [ a ] 0 1 0 0 3 1 0 s 6 b p 2 0 2 a g r a p h 0 0 4 - 1 2 0 4 0 5 0 6 0 7 0 e f f i c i e n c y ( f i x e d p w m ) 3 0 8 0 9 0 1 0 . 1 0 . 0 0 1 v v i n = 2 . 5 v v v i n = 4 . 5 v v v i n = 4 2 v 0 . 0 1 l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , v v i n = 1 2 v e f f i c i e n c y [ % ] l o a d c u r r e n t [ a ] 0 1 0 0 3 1 0 s 6 b p 2 0 2 a g r a p h 0 0 4 - 2 2 0 4 0 5 0 6 0 7 0 e f f i c i e n c y ( a u t o m a t i c p w m / p f m ) 3 0 8 0 9 0 1 0 . 1 0 . 0 0 1 v v i n = 4 2 v v v i n = 1 2 v v v i n = 4 . 5 v v v i n = 2 . 5 v 0 . 0 1 l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l o a d c u r r e n t [ a ] 2 . 5 s 6 b p 2 0 2 a g r a p h 0 0 5 l o a d r e g u l a t i o n ( f i x e d p w m ) 2 . 0 1 . 5 1 . 0 0 . 5 0 t a = + 1 2 5 o c t a = + 2 5 o c t a = o c l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v i n = 1 2 v , v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , v v o u t [ v ] 4 . 9 2 4 . 9 8 4 . 9 6 4 . 9 4 5 . 0 0 5 . 0 4 5 . 0 6 5 . 0 8 5 . 0 2 v v i n [ v ] 4 5 s 6 b p 2 0 2 a g r a p h 0 0 6 l i n e r e g u l a t i o n ( f i x e d p w m ) 3 5 2 5 1 5 1 0 0 t a = + 1 2 5 o c , l o a d c u r r e n t = 1 . 5 a 5 2 0 3 0 4 0 l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l o a d c u r r e n t = 2 . 4 a t a = o c , l o a d c u r r e n t = 2 . 4 a v v o u t [ v ] 4 . 9 2 4 . 9 8 4 . 9 6 4 . 9 4 5 . 0 0 5 . 0 4 5 . 0 6 5 . 0 8 5 . 0 2 i v i n q [ a ] 0 6 0 i v i n q v s v v i n ( a u t o m a t i c p w m / p f m ) 4 0 2 0 8 0 1 0 0 1 2 0 1 4 0 t a = o c v v i n [ v ] s 6 b p 2 0 2 a g r a p h 0 0 8 - 1 4 5 1 0 0 2 0 2 5 4 0 5 1 5 3 0 3 5 t a = + 2 5 o c t a = + 1 2 5 o c l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v o u t = 5 v , l o a d c u r r e n t = 0 a , f o s c = 2 . 1 m h z s e t , 2 m s / d i v e n a 5 v / d i v v o u t 5 v / d i v l x 1 2 a / d i v p g 5 v / d i v v c c 5 v / d i v t u r n o f f r e s p o n s e 2 m s / d i v s 6 b p 2 0 2 a g r a p h 0 0 9 - 1 e n a 5 v / d i v v o u t 5 v / d i v l x 1 2 a / d i v p g 5 v / d i v v c c 5 v / d i v t u r n o n r e s p o n s e t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f s 6 b p 2 0 2 a g r a p h 0 0 9 - 2 a u t o m a t i c p w m / p f m a u t o m a t i c p w m / p f m v v i n = 1 2 v , v v o u t = 5 v , l o a d c u r r e n t = 0 a , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v i n = 1 2 v , v v o u t = 5 v , l o a d c u r r e n t = 0 a , f o s c = 2 . 1 m h z s e t ,
document number: 002 - 08496 rev. *d page 16 of 20 s6bp202a s 6 b p 2 0 2 a g r a p h 0 1 0 - 2 2 0 0 s / d i v l o a d t r a n s i e n t r e s p o n s e s 6 b p 2 0 2 a g r a p h 0 1 0 - 1 2 0 0 s / d i v v o u t 2 0 0 m v / d i v l o a d c u r r e n t 1 a / d i v p g 5 v / d i v a u t o m a t i c p w m / p f m a u t o m a t i c p w m / p f m l o a d t r a n s i e n t r e s p o n s e a c - c o u p l e d 1 a / d i v p g 5 v / d i v v o u t 2 0 0 m v / d i v a c - c o u p l e d / 1 0 s / 1 0 s l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v i n = 1 2 v , v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l o a d c u r r e n t l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v i n = 1 2 v , v v o u t = 5 v , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , 0 a 2 . 4 a 2 . 4 a 0 a s 6 b p 2 0 2 a g r a p h 0 1 1 - 2 1 m s / d i v v i n 1 0 v / d i v v o u t 2 0 0 m v / d i v p g 5 v / d i v c o l d c r a n k l i n e t r a n s i e n t r e s p o n s e l o a d d u m p l i n e t r a n s i e n t r e s p o n s e a c - c o u p l e d a u t o m a t i c p w m / p f m s 6 b p 2 0 2 a g r a p h 0 1 1 - 1 4 m s / d i v v i n 2 v / d i v v o u t 2 0 0 m v / d i v p g 5 v / d i v a c - c o u p l e d a u t o m a t i c p w m / p f m 2 . 5 v 6 v / 1 m s / 1 m s 1 1 v 2 . 5 v v v o u t = 5 v , l o a d c u r r e n t = 0 . 2 a , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v o u t = 5 v , l o a d c u r r e n t = 2 . 4 a , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f 4 0 v 1 1 v / 1 m s 1 1 v 4 0 v / 1 m s 1 0 m s / d i v s 6 b p 2 0 2 a g r a p h 0 1 2 - 2 r i p p l e w a v e f o r m 1 s / d i v s 6 b p 2 0 2 a g r a p h 0 1 2 - 1 l x 1 2 v / d i v s w i t c h i n g w a v e f o r m v o u t 5 0 m v / d i v a u t o m a t i c p w m / p f m a u t o m a t i c p w m / p f m a c - c o u p l e d v v i n = 1 2 v , v v o u t = 5 v , l o a d c u r r e n t = 2 . 4 a , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f v v i n = 1 2 v , v v o u t = 5 v , l o a d c u r r e n t = 0 a , f o s c = 2 . 1 m h z s e t , t a = + 2 5 o c , l l x = 2 . 2 h , c v o u t _ 1 = c v o u t _ 2 = 2 2 f
document number: 002 - 08496 rev. *d page 17 of 20 s6bp202a 12. usage precaution printed circuit board ground lines should be set up with consideration for common impedance. take appropriate measures against static electricity. ? containers for semiconductor materials should have anti?static protection or be made of conductive material. ? after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. ? work platforms, tools, and instruments should be properly grounded . ? working personnel should be grounded with r esistance of 250 k to 1 m in s erial body and ground . do not apply negative voltages. the use of negative voltages below ?0.3 v may make the parasitic transistor activated to the lsi, and can cause malfunctions. 13. rohs compliance information th is product has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (pbb), and polybrominated diphenyl ethers (pbde) . 14. ordering information table 14 - 1 ordering information order code part n umber (mpn) (*1) package 1f s6bp202a1fst2b00 a p lastic e tssop16 ( 0. 6 5 mm p itch) , 16 - pin ( package code: sec016 ) 1g s6bp202a1gst2b00a 4f s6bp202a4fst2b00a 7f s6bp202a7fst2b00a mpn: marketing part number * 1: please contact our sales division for the part numbers (refer to " 1 . product lineup ") not mentioned in this table. figure 14 - 1 ordering part number definitions s 6 b p 2 0 2 a x x s t 2 b 0 0 a f i x e d o n 0 0 a p a c k i n g : b = 1 3 i n c h t a p e a n d r e e l p a c k a g e : t 2 = e t s s o p , p u r e s n / l o w - h a l o g e n r e l i a b i l i t y g r a d e : s = 1 0 p p m p r e s e t c o n d i t i o n ( o r d e r c o d e ) : s e e p r o d u c t l i n e u p r e v i s i o n : a = 1 s t r e v i s i o n p r o d u c t i d : 0 2 t o p o l o g y : 2 = s w i t c h - m o d e p o w e r s u p p l y ( i n t e g r a t e d f e t ) p r o d u c t t y p e : p = p o w e r m a n a g e m e n t i c p r o d u c t c l a s s : 6 b = a u t o m o t i v e a n a l o g c o m p a n y i d : s = c y p r e s s
document number: 002 - 08496 rev. *d page 18 of 20 s6bp202a 15. package dimensions p a c k a g e c o d e : s e c 0 1 6 0 0 2 - 1 0 7 6 9 r e v . * *
document number: 002 - 08496 rev. *d page 19 of 20 s6bp202a 16. m ajor c hanges spansion publication number: s6bp202a_ds405 - 00027 page section change results preliminary 0.1 ? ? initial release preliminary 0.2 1 c over page the sentences of the "notice to readers" w ere changed from "the contents of full production" to "the contents of preliminary". 13 10. electrical characteristics "(tsd)" was added in the table of " 10. electrical characteristics " . note: please see document history ab out later revised information. document history document title: s6bp202a, assp, 42v, 2.4a, synchronous buck - boost dc/dc converter ic document number: 002 - 08496 revision ecn orig. of change submission date description of change ** ? hixt 0 9 / 04 /2015 new spec. * a 5056149 hixt 12/ 18 /2015 added block diagram added figure 15 - 1 updated 16. package dimensions * b 5164343 hixt 03/ 0 8 /2016 added aec - q100 compliant (grade - 1) in features added figure 3 - 1 i/o pin equivalent circuit diagram the followings in 7. electrical characteristics were updated. the parameter name of i vout was changed from vout output voltage to maximum output current the max values of i vout were moved to the min column. added 11. development support added 12. reference data deleted the es part number from table 15 - 1 * c 5839054 masg 07/31/2017 adapted cypress new logo. *d 5 909405 hixt 10/ 1 3 / 2017 updated to the cypress naming and format updated tssop ? etssop in features , table 14 - 1 and figure 14 - 1 updated 15 package dimensions a dded more information deleted 11. development support (moved to more information ) changed the suffix of the part number from 000 to 00a in 1 . product lineup table 14 - 1 and figure 14 - 1
document number: 002 - 08496 rev. *d october 13, 2017 page 20 of 20 s6bp202a sales, solutions, and legal informa tion worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress. com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power managemen t ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | co mp onents technical support cypress.com/support arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the us and/or elsewhere. ? cypress semiconductor corporation, 201 5 - 2017. this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress). this document, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ectual property laws and treaties of the unit ed states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this para graph, grant any license under its patents, copyrights, trademarks, or other intellectual property ri ghts. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypre ss governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without th e right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your or ganization, and (b) to di stribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardwar e product units, and (2) under those claims of cypresss patents that are infringed by th e software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the e xtent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit describ ed in this document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and t est the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope ration of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution con trol or hazardous substances management, or other uses where the failure of t he device or system could cause personal injury, death, or property damage (unintended uses). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, o r to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cyp ress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall ind e mnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. othe r names and brands may be claimed as property of their respective owners.

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